This patent application is a United States counterpart to and claims the benefit of the priority date of European Patent Application No. 98830461.4 filed on Jul. 30, 1998, which is hereby incorporated by reference.
This invention relates to a semiconductor circuit structure comprising a parasitic transistor with a very high threshold voltage.
As is well known, the need to have an ever larger number of devices integrated in one chip has led to a significant reduction in the thickness of the field and isolation oxides which define the active areas of devices provided in the chip.
More generally, during the fabrication process of different devices, successive oxide removing steps are to be carried out in order to produce oxide layers having different thicknesses. This requirement becomes more difficult to meet where transistors capable of standing high voltages are to be provided on the same chip which accommodates low voltage transistors.
Such successive oxide layer-removing steps also affect the isolation oxide layers. This results in further thinning of the thick (isolation) oxides, and attendant lowering of the threshold voltage of the parasitic transistors which form between adjacent devices. Such lowering is often undesirable. Therefore, there is a need for a circuit structure that overcomes these shortcomings in the prior art.
Briefly, according to the invention, a circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors, each formed in a respective active area region of the semiconductor substrate. Each transistor has a source region, a drain region, and a channel region located between the source and drain regions and being overlaid by a gate region. The gate regions of the transistor pair are connected electrically together by an overlying conductive layer and respective contacts, wherein the contacts between the gate regions and the conductive layer are formed above the active areas.
FIG. 1 is an enlarged top plan view showing schematically a portion of a semiconductor wherein a first embodiment of a prior art circuit structure has been formed.
FIG. 2 is an enlarged vertical cross-section view, taken along line 11xe2x80x9411 in FIG. 1, showing schematically the first embodiment of a prior art circuit structure.
FIG. 3 is an enlarged top plan view showing schematically a portion of a semiconductor wherein a second embodiment of a prior art circuit structure has been formed.
FIG. 4 is an enlarged vertical cross-section view, taken along line IVxe2x80x94IV in FIG. 3, showing schematically the second embodiment of a prior art circuit structure.
FIG. 5 is an enlarged top plan view showing schematically a portion of a semiconductor wherein a first embodiment of the circuit structure according to the invention has been formed.
FIG. 6 is an enlarged vertical cross-section view, taken along line VIxe2x80x94VI in FIG. 3, showing schematically the first embodiment of the circuit structure according to the invention.
FIG. 7 is an enlarged top plan view showing schematically a portion of a semiconductor wherein a second embodiment of the circuit structure according to the invention has been formed.
FIG. 8 is an enlarged vertical cross-section view, taken along line VIIIxe2x80x94VIII in FIG. 7, showing schematically the second embodiment of the circuit structure according to the invention.
FIG. 9 is an enlarged vertical cross-section view, taken along line IXxe2x80x94IX in FIG. 7, showing schematically the second embodiment of the circuit structure according to the invention.